1. Field of the Invention
The invention relates to a method for processing substrates, such as semiconductor wafers, and more particularly, to a method for wet oxidizing a dielectric material disposed on a substrate.
2. Description of the Related Art
Reliably producing sub-half micron and smaller features is one of the key technologies for the next generation of very large scale integration (VLSI) and ultra large-scale integration (ULSI) of semiconductor devices. However, as the limits of integrated circuit technology are pushed, the shrinking dimensions of interconnects in VLSI and ULSI technology have placed additional demands on processing capabilities. Integrated circuits may include more than one million micro-electronic field effect transistors (e.g., complementary metal-oxide-semiconductor (CMOS) field effect transistors) that are formed on a substrate (e.g., semiconductor wafer) and cooperate to perform various functions within the circuit. Reliable formation of the gate pattern and shallow trench isolation (STI) regions are important to integrated circuits success and to the continued effort to increase circuit density and quality of individual substrates and die. In order to achieve greater circuit density, not only must device feature size be reduced, but the size of isolation structures between devices must be reduced as well.
Current isolation techniques include shallow trench isolation (STI) processes. STI processes include first etching a trench having a predetermined width and depth into a substrate. The trench is then filled with a layer of dielectric material. The dielectric material is then planarized by, for example, chemical-mechanical polishing (CMP) process.
As the width of trenches continues to shrink, the aspect ratio (depth divided by width) continues to grow. One challenge regarding the manufacture of high aspect ratio trenches is avoiding the formation of voids during the deposition of dielectric material in the trenches.
To fill a trench, a layer of dielectric material, such as silicon oxide, is deposited. The dielectric layer typically covers the field, as well as the walls and the bottom of the trench. If the trench is wide and shallow, it is relatively easy to completely fill the trench. However, as the aspect ratio increases, it becomes more likely that the opening of the trench will “pinch off”, forming a void within the trench.
To decrease the likelihood of forming a void within the trench or forming seams within the trench, many different process techniques have been developed to fill in the trench with the dielectric materials without defects. For example, a conventional spray coating process may be used to fill in the trench with a liquid precursor to form a void-free or seam-free dielectric material in the trench. After the liquid precursor fills the trench, a high temperature annealing process is typically performed to drive out the moisture from the liquid precursor, thereby forming a dielectric material within the trench in a solid phase. However, this deposition technique often suffers from high film impurities as the liquid precursor used to fill in the trench may include contaminants that may adversely deteriorate on the electrical properties of the formed dielectric material which adversely affects device performance.
In another example, high aspect ratio processes (HARP) may be used to form the dielectric material. These processes include depositing the dielectric material at different rates during different stages of the deposition process. A lower deposition rate may be used to form a more conformal dielectric layer in the trench, and a higher deposition rate may be used to form a bulk dielectric layer above the trench. However, HARP processes often have low throughput, which results in high manufacturing cost.
Therefore, a need exists for improvements in processes and apparatus for producing high aspect ratio isolation structures.